This new guide covers the key design problems of modeling, architectural tradeoffs, functional verification, timing analysis, test generation, fault simulation, design for testability, logic synthesis, and postsynthesis verification. The author's focus is on developing, verifying, and synthesizing designs of digital circuits rather than on the Verilog language.
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This new guide covers the key design problems of modeling, architectural tradeoffs, functional verification, timing analysis, test generation, fault simulation, design for testability, logic synthesis, and postsynthesis verification. The author's focus is on developing, verifying, and synthesizing designs of digital circuits rather than on the Verilog language.
Read Less
