As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the - minishing fabrication process features, which a?ect for example the gate-to-wire delay ratio. They manifest themselves in greater variations of size and operating parameters of devices, which put the overall reliability of systems at risk. And, most of all, they have tremendous impact on design productivity, where the costs of utilizing the growing silicon 'real estate' rocket ...
Read More
As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the - minishing fabrication process features, which a?ect for example the gate-to-wire delay ratio. They manifest themselves in greater variations of size and operating parameters of devices, which put the overall reliability of systems at risk. And, most of all, they have tremendous impact on design productivity, where the costs of utilizing the growing silicon 'real estate' rocket to billions of dollars that have to be spent on design, veri?cation, and testing. All such problems call for new - sign approaches and models for digital systems. Furthermore, new developments in non-CMOS technologies, such as single-electron transistors, rapid single-?- quantum devices, quantum dot cells, molecular devices, etc., add extra demand for new research in system design methodologies. What kind of models and design methodologies will be required to build systems in all these new technologies? Answering this question, even for each particular type of new technology generation, is not easy, especially because sometimes it is not even clear what kind of elementary devices are feasible there. This problem is of an interdisciplinary nature. It requires an bridges between di?erent scienti?c communities. The bridges must be built very quickly, and be maximally ?exible to accommodate changes taking place in a logarithmic timescale.
Read Less
Add this copy of Concurrency and Hardware Design to cart. $51.19, very good condition, Sold by GuthrieBooks rated 5.0 out of 5 stars, ships from Spring Branch, TX, UNITED STATES, published 2003 by Springer.
Add this copy of Concurrency and Hardware Design: Advances in Petri Nets to cart. $51.18, like new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 2002 by Springer.
Choose your shipping method in Checkout. Costs may vary based on destination.
Seller's Description:
Fine. Trade paperback (US). Glued binding. 346 p. Lecture Notes in Computer Science, 2549. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
Add this copy of Concurrency and Hardware Design: Advances in Petri Nets to cart. $51.64, new condition, Sold by GreatBookPrices rated 4.0 out of 5 stars, ships from Columbia, MD, UNITED STATES, published 2002 by Springer.
Choose your shipping method in Checkout. Costs may vary based on destination.
Seller's Description:
New. Trade paperback (US). Glued binding. 346 p. Lecture Notes in Computer Science, 2549. In Stock. 100% Money Back Guarantee. Brand New, Perfect Condition, allow 4-14 business days for standard shipping. To Alaska, Hawaii, U.S. protectorate, P.O. box, and APO/FPO addresses allow 4-28 business days for Standard shipping. No expedited shipping. All orders placed with expedited shipping will be cancelled. Over 3, 000, 000 happy customers.
