Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Read More
Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Read Less
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $26.29, good condition, Sold by Greenworld Books rated 5.0 out of 5 stars, ships from Arlington, TX, UNITED STATES, published 2007 by Morgan Kaufmann.
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Seller's Description:
Good condition book with a firm cover and clean readable pages. Shows normal use including some light wear or limited notes highlighting yet remains a dependable copy overall. Supplemental items like CDs or access codes may not be included.
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $27.39, good condition, Sold by BooksRun rated 4.0 out of 5 stars, ships from Philadelphia, PA, UNITED STATES, published 2007 by Morgan Kaufmann.
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Good. It's a well-cared-for item that has seen limited use. The item may show minor signs of wear. All the text is legible, with all pages included. It may have slight markings and/or highlighting.
Add this copy of System-on-Chip Test Architectures: Nanometer Design for to cart. $81.15, good condition, Sold by Bonita rated 4.0 out of 5 stars, ships from Santa Clarita, CA, UNITED STATES, published 2007 by Morgan Kaufmann.
